A memory device is usually controlled by a memory controller, which, by sending commands to the memory device, can control, for example, the operations of the memory device, such as reading or writing of the memory device. For a memory device, especially a serial peripheral interface (SPI) memory device, a command may be generated as a series of binary digits, i.e., a series of 0's and 1's. For some types of memory devices, the command may be coded using 8 binary digits, which may therefore be referred to as an 8-bit command. For example, a D35H command includes the series of binary digits 00110101, which represents a read command. As a further example, a D75H command includes the series of binary digits 01110101, which represents a write command.
FIG. 1 schematically shows exemplary signal waveforms, including a command as would be applied to a memory controller. In FIG. 1, CSB stands for “Chip Select Bar,” which controls when a command is asserted for a certain chip. SIO stands for “Serial Input/Output,” which represents the command entered into the memory controller. In the example shown in FIG. 1, the input command is the D35H command which, as described above, includes the series of binary digits 00110101. Further, in FIG. 1, SCLK stands for “Serial Clock.”
The memory controller receiving the signal waveforms in FIG. 1 is a single-data-rate controller, which means that the command applied to the memory controller is received and transferred to the memory at rising edges of the clock signal, i.e., SCLK shown in FIG. 1. For example, at the first rising edge of SCLK, SIO is at a low logic voltage level, and thus a low logic voltage level, which represents binary digit “0”, is received by the controller and transferred to the memory. Further, for example, at the third rising edge of SCLK, SIO is at a high logic voltage level, and thus a high logic voltage level, which represents binary digit “1”, is received by the controller and transferred to the memory. Therefore, if the memory controller operates correctly, the SIO signal is received, i.e., sampled, at a timing corresponding to the clock signal, and transferred to the memory as the correct command, i.e., the D35H command, i.e., a reading command, including a series of binary digits of 00110101.
However, in a high-speed application, each signal needs to switch between high and low logic voltage levels at a high frequency. In such a case, a signal may not switch at the exact timing that it should switch. For example, the SIO signal may not switch at the correct timing, or the SCLK signal may not switch at the correct timing. As a result, the SIO signal may be received, i.e., sampled, at an incorrect time.
For example, due to the high-speed switching, the SIO signal may switch from the low logic voltage level to the high logic voltage level earlier than it is designed to switch, as indicated by the dashed line in FIG. 1. As a result, at the second rising edge of the SCLK signal, when the memory controller samples the logic voltage level of the SIO signal, a high logic voltage level is received and transferred to the memory device, rather than a low logic voltage level as intended. Therefore, instead of receiving the D35H command, which represents a read command, the memory device receives the D75H command including the series of binary digits 01110101, which represents a write command. As a result, the data stored on the memory device are incorrectly erased.